Step 3: Synthesizing the Design - 2020.2 English

Vivado Design Suite Tutorial: Dynamic Function eXchange

Document ID
Release Date
2020.2 English

The run_synth.tcl script automates the synthesis phase of this tutorial. Seven iterations of synthesis are called, one for the static top-level design, two for the first-order Reconfigurable Modules, and four for the second-order Reconfigurable Modules.

  1. Open the Vivado Tcl shell:

    On Windows, select the Xilinx Vivado desktop icon or Start > All Programs > Xilinx Design Tools> Vivado 2020.2 > Vivado 2020.2 Tcl Shell.

    On Linux, type: vivado -mode tcl.

  2. In the shell, navigate to the <Extract_Dir>directory.
  3. Confirm the target board is selected by the xboard variable in run_synth.tcl.
  4. Run the run_synth.tcl script by entering:
    source run_synth.tcl -notrace 

After all the seven passes through Vivado Synthesis have completed, the Vivado Tcl shell is left open. You can find log and report files for each module, alongside the final checkpoints, under each named folder in the Synth subdirectory.

Tip: In the <Extract_Dir> directory, multiple log files have been created:
  1. run.log shows the summary as posted in the Tcl shell window
  2. command.log echoes all the individual steps run by the script
  3. critical.log reports all critical warnings produced during the run