Batch Simulation - 2020.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2021-02-12
Version
2020.2 English
Recommended: If your verification environment has a self-checking test bench, run simulation in batch mode. There is a significant runtime cost when you view simulator waveforms using the integrated simulation.

For batch simulation, the Vivado Design Suite provides the export_simulation Tcl command to generate simulation scripts for supported simulators, including the Vivado simulator. You can use the scripts generated by export_simulation directly or use the scripts as a reference for building your own custom simulation scripts.

The export_simulation command creates separate scripts for each stage of the simulation process (compile, elaborate, and simulate) so that you can easily incorporate the generated scripts in your own verification flow. For more information about generating scripts for batch simulation, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).