PCB Design Considerations - 2020.2 English

Versal ACAP Board System Design Methodology Guide (UG1506)

Document ID
Release Date
2020.2 English
The PCB should be designed considering the fastest signal interfacing with the device. These high-speed signals are extremely sensitive to trace geometry, vias, loss, and crosstalk. These aspects become even more prominent for multi-layer PCBs. For high-speed interfaces perform a signal integrity simulation. A board redesign with improved PCB material or altered trace geometries may be necessary to obtain the desired performance.

Xilinx recommends following these steps when designing your PCB:

  1. Review the following device documentation:
    • Power, memory, and MIO interface guidelines in the Versal ACAP PCB Design User Guide (UG863).
    • Board Design Guidelines in the Versal ACAP GTY Transceivers Architecture Manual (AM002)
  2. Review memory IP and PCIe® design guidelines in the IP product guides.
  3. Use the Vivado tools to validate your I/O planning:
    • Run simultaneous switching noise (SSN) analysis.
    • Run built-in DRCs.
    • Export I/O buffer information specification (IBIS) models.
  4. Run signal integrity analysis as follows:
    • For gigabit transceivers (GTs), run Spice or IBIS-AMI simulations using channel parameters.
    • For lower performance interfaces, run IBIS simulation to check for issues with overshoot or undershoot.
  5. Use the XPE with Process set to Maximum to generate an early estimate of the power consumption for the design.
  6. Complete and adhere to the schematic checklist for your device.
    Note: See the Versal ACAP Schematic Review Checklist (XTP546).
  7. Manually add XDC constraints to your XDC file for the Vivado tools.