Gigabit Transceivers (GTs) - 2020.2 English

Versal ACAP Board System Design Methodology Guide (UG1506)

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2020.2 English

Gigabit transceivers (GTs) have specific pinout requirements, and you must consider the following:

  • Sharing of reference clocks
  • Sharing of PLLs within a quad
  • Placement of GT hard blocks such as PCIe or MRMAC, and their proximity to transceivers

Xilinx recommends that you use the GT wizard to generate the core. Alternatively, you can use the Xilinx IP core for the protocol. For pinout recommendations, see the related product guide.