Congestion can be caused by a variety of factors and is a complex problem that
does not always have a straightforward solution. The report_design_analysis congestion report helps you identify the congested
regions and the top modules that are contained within the congestion window. Various
techniques exist to optimize the modules in the congested region. The
report_qor_suggestions can automate the resolution of many of the
items that cause congestion.
Tip: Before you try to address congestion
with the techniques being discussed below, make sure that you have clean constraints and
have followed Xilinx clocking guidelines. Excessive hold time failures (or negative hold
slack) and clock uncertainties require the router to detour which can lead to
congestion. Overlapping Pblocks can also cause congestion and should be avoided.