Versal ACAP System Integration and Validation Methodology Guide (UG1388) - 2020.2 English

Document ID: UG1388
Release Date: 2021-02-04
Version: 2020.2 English

Revision History
Introduction
About the Versal ACAP Design Methodology
Navigating Content by Design Process
About This Guide
Simulation Flows
Embedded Software Simulation
Logic Simulation
Logic Simulation Using SystemC Models
HLS Simulation
AI Engine Simulation
Hardware Emulation
Design Closure
Timing Closure
Understanding Timing Closure Criteria
Checking for Valid Constraints
Checking for Positive Timing Slacks
Understanding Timing Reports
Checking That Your Design is Properly Constrained
Fixing Issues Flagged by check_timing
No Clock and Unconstrained Internal Endpoints
Generated Clocks
Loops and Latch Loops
No Input/Output Delays and Partial Input/Output Delays
Multiple Clocks
Fixing Issues Flagged by report_methodology
Methodology DRCs with Impact on Timing Closure
Methodology DRCs with Impact on Signoff Quality
Other Timing Methodology DRCs
Assessing the Maximum Frequency of the Design
Baselining the Design
Defining Baseline Constraints
Identifying Which Clocks Must be Created
Verifying That No Clocks Are Missing
Constraining Clock Domain Crossings
Reviewing Clock Relationships
Identifying Clock Pairs Without Common Primary Clocks
Identifying Tight Timing Requirements
Constraining Both Primary and Generated Clocks at the Same Time
Limiting I/O Constraints and Timing Exceptions
Evaluating Design WNS After Each Step
Post-Synthesis and Post-Logic Optimization
Pre- and Post-Placement
Pre- and Post-Physical Optimization
Pre and Post-Route
Baselining and Timing Constraints Validation Procedure
Analyzing and Resolving Timing Violations
Identifying Timing Violations Root Cause
Reviewing Timing Slack
Using the Design Analysis Report
Analyze Path Characteristics
Review the Logic Level Distribution
Datapath Delay and Logic Levels
Clock Skew and Uncertainty
Reducing Logic Delay
Optimizing Regular Fabric Paths
Optimizing Paths with Dedicated Blocks and Macro Primitives
Reducing Net Delay Caused by Physical Constraints
Reducing Net Delay Caused by Congestion
Congestion Area and Level Definition
Congestion Level Ranges
Interconnect Congestion Level in the Device Window
Congestion in the Placer Log
Congestion in the Router Log
Report Design Analysis Congestion Report
Report Design Analysis Complexity Report
Reducing Clock Skew
Using Intra-Clock Timing Paths
Adding Timing Exceptions between Asynchronous Clocks
Applying Common Techniques for Reducing Clock Skew
Improving Skew in Versal Devices
Reducing Clock Uncertainty
Using MMCM Settings to Reduce Clock Uncertainty
Using MBUFGCE to Reduce Clock Uncertainty
Applying Common Timing Closure Techniques
Improving the Netlist with Block-Level Synthesis Strategies
Improving Logic Levels
Reducing Control Sets
Follow Control Set Guidelines
Reduce the Number of Control Sets
Optimizing High Fanout Nets
Allow Register Replication
Promote High Fanout Nets to Global Routing
Use Physical Optimization
Prioritize Critical Logic Using the group_path Command
Fixing Large Hold Violations Prior to Routing
Addressing Congestion
Lower Device Utilization
Use Alternate Placer and Router Directives
Turn Off Cross-Boundary Optimization
Disable LUT Combining
Limit High-Fanout Nets in Congested Areas
Use Cell Bloating
Tuning the Compilation Flow
Using Strategies and Directives
Predefined Strategies
Custom Strategies
Using Optimization Iterations
Overconstraining the Design
Considering Floorplan
Grouping Critical Logic
Reusing Placement Results
XPIO-PL Interface Techniques for Timing
AI Engine-PL Interface Techniques for Timing
Power Closure
Estimating Power Throughout the Flow
Recommended Power Constraints
Best Practices for Accurate Power Analysis
Reviewing the Design Power Distribution After Running Power Analysis
System Performance Closure
Analyzing System Performance for Platform Designs
Analyzing System Performance in Simulation
Analyzing AI Engine Performance in Simulation
Analyzing PL Kernel Performance in Simulation
Using Hardware Emulation to Analyze System Performance
Analyzing System Performance in Hardware
Measuring Performance with RTL or HLS Monitors
Measuring AI Engine Performance
Measuring Performance with AI Engine Run Time Event APIs
Measuring Performance with Event Trace Debug
Debugging AI Engine-PL Performance on Silicon
Improving Performance in the PS
Improving Performance in the PL
Reducing Latency
Addressing Floorplanning Impact on Performance
Improving Performance Through the NoC
Improving Performance in the AI Engine
Improving Performance Through the CPM and PL PCIe
I/O Behaviors and Routes
Performance Setup
Debug Steps
Limitations
Configuration and Debug
Configuration
Debugging
Debugging the PS/PMC
JTAG Status and Error Status
Rails Voltage Status
PS/PMC Peripheral Resets
PS/PMC Clocks
Debugging the AI Engine
Debugging with SmartLynq+
Debugging the PL
AXI4 Debug Hub Connectivity
Using ILA Cores
Probing the Design
Choosing Debug Nets
Retaining Names of Debug Probe Nets Using MARK_DEBUG
ILA Core and Timing Considerations
ILA Core Designs with High-Speed Clocks
Using VIO Cores
VIO Core Considerations
Debugging AXI Interfaces in Vivado Hardware Manager
Using IBERT GTY for Transceiver Link Characterization
Running Debug-Related DRCs
Generating AXI Transactions
Modifying the Implemented Netlist to Replace Existing Debug Probes
Inserting, Deleting, or Editing ILA Cores on an Implemented Netlist
Connecting a Net to a Free External Pin Using Post-Route ECO
Using Remote Debugging
Validation
Block and IP Validation
Generator and Checkers
AI Engine Design Validation
Functional Validation
Performance Validation
System Validation
Design Debug
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
References
Vivado Design Suite User and Reference Guides
Vivado Design Suite Tutorials
Other Xilinx Documentation
Training Resources
Please Read: Important Legal Notices

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