The
Vivado®
IP integrator enables the creation of block
designs (.bd) or IP subsystems with multiple IP
stitched together using SmartConnect IP and the NoC. The IP integrator lets you:
- Connect IP cores to create domain-specific subsystems and designs
- Instantiate high-level synthesis modules from Vitis™ HLS, DSP modules from System Generator, and custom user-defined IP
Using the IP integrator, you can drag and drop IP onto the design canvas, connect AXI interfaces with one wire, and place ports and interface ports to connect the IP subsystem to the top-level design. These IP block designs can also be packaged as sources (.bd) and reused in other designs. For more information, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) and Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898).
Note: As part of design
creation, design constraints must be reviewed and completed in the Vivado Design Suite after running synthesis.
Important: This section describes how
to create a hardware design using the
Vivado®
IP
integrator. This is the primary design type for non-AI Engine-based projects. A platform design is similar but allows the
Vitis™
linker to add additional PL and
AI Engine blocks to the design, which is
required for AI Engine-based projects and can also
be used for non-AI Engine-based projects. Creating a
platform design has additional requirements, as described in the
Vitis Embedded Software
Development Flow Documentation in the Vitis Unified Software Platform
Documentation (UG1416).