The CIPS IP core configures the following hardware features:
- Processing system (PS)
- Boot mode settings for the device
- Debug interfaces between CIPS and PL
- Platform management controller (PMC)
- Interconnect for Cache Coherent Interconnect for Accelerators (CCIX) and PCIe® module (CPM)
- System monitor (SYSMON) controller
- Single event mitigation (SEM) controller
- Interfaces between the PS-NoC/DDRMC
- Interfaces between the PS-PL
Note: Only a single CIPS
IP is allowed per design.
For descriptions of the PMC and PS, see the Versal ACAP Technical Reference Manual (AM011). For information on CIPS IP, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352). For information on the CPM, see the Versal ACAP CPM CCIX Architecture Manual (AM016) and Versal ACAP CPM Mode for PCI Express Product Guide (PG346).