LogiCORE IP Facts Table | |
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Core Specifics | |
Supported Device Family 1 |
Zynq® UltraScale+™ MPSoC, UltraScale™ , UltraScale+™ 7 series Versal™ ACAP |
Supported User Interfaces | AXI4-Lite, AXI4-Stream |
Resources | Performance and Resource Utilization web page (registration required) |
Provided with Core | |
Design Files | N/A |
Example Design | IP integrator Block Diagram |
Test Bench | Verilog |
Constraints File | Not Provided |
Simulation Model |
System Verilog SecureIP model Bit-accurate C model MEX file for use with MATLAB |
Supported S/W Driver 2 |
Standalone |
Tested Design Flows 3 | |
Design Entry | Vivado® Design Suite |
Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide |
Synthesis | Vivado |
Support | |
Release Notes and Known Issues | Master Answer Record: 69399 |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Xilinx Support web page | |
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