DPUCVDX8G Port Description - 1.2 English

DPUCVDX8G for Versal ACAPs Product Guide (PG389)
Document ID
PG389
Release Date
2022-06-24
Version
1.2 English

Ports are available from the DPUCVDX8G to the NoC and the PS. The interface from the PS to the DPUCVDX8G PL component is used for register configuration. The interfaces from the DPUCVDX8G PL component to the NoC are for image and weight transfers. The interfaces from the PL component to the AI Engine component are for intermediate data exchange. The DPUCVDX8G top-level interfaces are shown in the following figure.

Figure 1. Connections from DPUCVDX8G to PS and NoC

There are parameters to configure the DPUCVDX8G architecture. The data width and number of different DPUCVDX8G interfaces differs for each architecture. A screen capture of DPUCVDX8G IP catalog with C32B1CU1 (CPB_N=32, CU_N=1) architecture is shown below:

Figure 2. DPUCVDX8G Ports with C32B1CU1 Arch
Table 1. DPUCVDX8G Port Description
Port Name Interface Type Data Width I/O Description
m_axi_aclk Clock 1 I Input clock used for DPUCVDX8G general logic.
m_axi_aresetn Reset 1 I Active-Low reset for DPUCVDX8G general logic.
s_axi_aclk Clock 1 I AXI clock input for S_AXI_CONTROL.
s_axi_aresetn Reset 1 I Active-Low reset for S_AXI_CONTROL.
interrupt Interrupt 1 O Active-High interrupt output from the DPUCVDX8G.
S_AXI_CONTROL AXI4-Lite 32 I/O 32-bit AXI4-Lite interface for the DPUCVDX8G registers.
Sxx_OFM_AXIS AXI4-Stream 64 I Output feature map from the AI Engine side to the PL side. The port number depends on the DPUCVDX8G architecture and the batch number.
Mxx_IFM_AXIS AXI4-Stream 128 O Input feature map from the PL side to the AI Engine side. The port number depends on the DPUCVDX8G architecture and batch number.
Mxx_WGT_AXIS AXI4-Stream 128 O Weights data from the PL side to the AI Engine side. The port number depends on the DPUCVDX8G architecture and batch number.
M00_INSTR_AXI AXI4 32 I/O 32-bit memory mapped AXI interface for DPU instructions.
M00_BIAS_AXI AXI4 128 I/O 128-bit memory mapped AXI interface for loading bias data.
Mxx_IMG_AXI AXI4 128 I/O 128-bit memory mapped AXI interface for loading image and uploading output. The port number depends on the DPUCVDX8G architecture and batch number.
Mxx_WGT_AXI AXI4 512 I/O 512-bit memory mapped AXI interface for loading shared weights. The port number is fixed at 4.