AP Registers - 1.2 English

The AP registers are general registers for the Vitis flow. The description of the AP registers are shown in the following table.

Table 1. AP Registers
Name	Offset Address	Bits	Filed Name	Type	Description
Control	0x00	[31:7]	Reserved		Reserved
		[6]	AP_RESET_DONE	r	The completion flag of soft reset. Active-High.
		[5]	AP_RESET	r/w	The soft reset for DPUCVDX8G. Active-High.
		[4]	Reserved		Reserved
		[3]	AP_READY	r	Indicates when the DPUCVDX8G is ready for new input data. Cleared on AP_DONE asserted.
		[2]	AP_IDLE	r	Asserted when the DPUCVDX8G is idle.
		[1]	AP_DONE	r	Asserted when the DPUCVDX8G has completed operation. Cleared on read.
		[0]	AP_START	r/w	Asserted when kernel can start processing data. Cleared on handshake with `ap_done` being asserted.
Global Interrupt Enable	0x04	[31:1]	Reserved		Reserved
Global Interrupt Enable	0x04	[0]	Global Interrupt Enable	r/w	Assert to enable interrupt
Interrupt Enable Register	0x08	[31:2]	Reserved		Reserved
		[1]	IER_AP_READY	r/w	The ap_ready of IER.
		[0]	IER_AP_DONE	r/w	The ap_done of IER.
Interrupt Status Register	0x0C	[31:2]	Reserved		Reserved
		[1]	ISR_AP_READY	r/w	The ap_ready of ISR.
		[0]	ISR_AP_DONE	r/w	The ap_done of ISR.

Control (0x0000) Register

This register controls the operation of the core.

Bit [0] of the Control register, ap_start, kicks off the IP from software. Writing 1 to this bit, starts the IP to working.
Bit [1] of the Control register, ap_done, indicates when the IP has completed all operations in the current transaction. A logic 1 on this signal indicates that the IP has completed all operations in this transaction.
Bit [2] of the Control register, ap_idle, signal indicates if the IP is operating or idle (no operation). The idle state is indicated by logic 1. This signal is asserted Low once the IP starts operating. This signal is asserted High when the IP completes operation and no further operations are performed.
Bit [3] of the Control register, ap_ready, signal indicates when the IP is ready for new inputs. It is set to logic 1 when the IP is ready to accept new inputs, indicating that all input reads for this transaction are completed. If the IP has no operations in the pipeline, new reads are not performed until the next transaction starts. This signal is used to make a decision on when to apply new values to the input ports and whether to start a new transaction.
Bit [5] of the Control register is the soft reset for the IP. When this is set, the IP is reset by the software.
Bit [6] of the Control register is the finished status of soft reset. This is asserted when the soft reset is done.

Global Interrupt Enable (0x0004) Register

This register is the master control for all interrupts. Bit [0] should be asserted to enable interrupt.

Interrupt Enable (0x0008) Register

This register allows interrupts to be enabled selectively. Currently, two interrupt sources are available, ap_done and ap_ready. ap_done is triggered after the IP processing is complete, while ap_ready is triggered after the IP is ready to start processing the next task.

Interrupt Status (0x000C) Register

This is a dual purpose register. When an interrupt occurs, the corresponding interrupt source bit is set in this register. In readback mode (Get status), the interrupting source can be determined. In writeback mode (Clear interrupt), the requested interrupt source bit is cleared.