Clock and Data Recovery Unit based on Deserialized Oversampled Data (XAPP1240)

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3.1 English

Multi-service networks require transceivers that can operate over a wide range of input data rates. High-speed serial I/O has a native lower limit data rate that prevents easy interfacing to low-speed client signals. The non-integer data recovery unit (NIDRU) presented in this application note extends the lower data rate limit to 0 Mb/s, making dedicated high-speed transceivers the ideal solution for true multirate serial interfaces. The NIDRU is specifically designed for the Xilinx® 7 series, UltraScale™, and Versal® devices. The NIDRU operational settings (data rate, jitter bandwidth, input ppm range, and jitter peaking) are dynamically programmable, avoiding the need for bitstream reload or partial reconfiguration. Operating on a synchronous external reference clock, the NIDRU supports fractional oversampling ratios. Thus, only one clock tree (BUFG or BUFG_GT) is needed, and is independent of the number of channels being set up, even if all channels are operating at different data rates.

The extracted data is delivered to the user application in parallel format. The width of this bus is programmable, thus simplifying the connection to both 8-bit and 10-bit applications.

At any time, without affecting the data traffic, a live horizontal eye scan can be performed to measure the real eye width as seen by the NIDRU. An eye scan controller, managing one or two extra phases, is embedded into the NIDRU wrapper.

You can download the reference design files for this application note from the Xilinx website. For detailed information about the design files, see Reference Design.