In scenario A, the design sets the ADC sampling rate to 2949.12 MSPS. According to the sampling theorem, all frequency content greater than the Nyquist frequency is aliased back to Nyquist zone 1, and as a result:
- The C-band baseband frequency at the ADC output lands at 750.88M – 1030.88 MHz.
- The PCS band baseband frequency at the ADC output lands at 959.12M – 1019.12 MHz.
The PCS band falls on top of the wanted C-band as illustrated in the following figure.
With the high performance of the AAF, the 16 dBm blocker at the ADC input is reduced to (again, referenced to the antenna input, and for ease of computation, assuming the total gain of the other components is the same at 1900M and 3800M):
16 dBm – 70 dB – 50 dB – 50 dB = –154 dBm
This is much lower than the target of –109 dBm. As the analysis shows, it is rather easy to handle the co-location blocker in the worst design scenario due to the availability of low-cost high-performance ceramic chip filters. It is not necessary to over design the cost sensitive antenna filter because it is far more efficient to filter the blocker in later stages of the RX chain. Without the optional BPF, the blocker aliased power would be –104 dBm. While this is sufficient to meet the 3GPP specification, it does not provide the desired margin. The optional BPF in this case provides ample design margin for minimal added cost.