MMI File Syntax - 2024.1 English

UpdateMEM User Guide (UG1580)

Document ID
UG1580
Release Date
2024-05-30
Version
2024.1 English

The MMI file is an XML file that syntactically describes how individual block RAMs make up a contiguous logical data space. You can create an MMI file from an open implemented design in the Vivado Design Suite using the write_mem_info Tcl command. The implemented design provides the needed placement information of the block RAM resources.

UpdateMEM uses the MMI file as input to direct the translation of data into the proper initialization form. The Example MMI file below shows the XML-based syntax used to describe the organization of block RAM usage.

<?xml version=”1.0” encoding=”UTF-8”?>
<MemInfo Version=”1” Minor=”0”>
  <Processor Endianness=”Little” InstPath=”design_1_i/microblaze_0”>
    <AddressSpace Name=”design_1_i_microblaze_0.design_1_i_microblaze_0_local_memory_dlmb_bram_if_cntlr” Begin=”0” End=”8191”>
      <BusBlock>
        <BitLane MemType=”RAMB32” Placement=”X2Y17”>
          <DataWidth MSB=”15” LSB=”0”/>
          <AddressRange Begin=”0” End=”2047”/>
          <Parity ON=”false” NumBits=”0”/>
        </BitLane>
        <BitLane MemType=”RAMB32” Placement=”X3Y17”>
          <DataWidth MSB=”31” LSB=”16”/>
          <AddressRange Begin=”0” End=”2047”/>
          <Parity ON=”false” NumBits=”0”/>
        </BitLane>
      </BusBlock>
    </AddressSpace>
 </Processor>
  <Processor Endianness=”Little” InstPath=”design_1_i/microblaze_1”>
    <AddressSpace Name=”design_1_i_microblaze_1.design_1_i_microblaze_1_local_memory_dlmb_bram_if_cntlr” Begin=”0” End=”8191”>
      <BusBlock>
        <BitLane MemType=”RAMB32” Placement=”X4Y13”>
          <DataWidth MSB=”15” LSB=”0”/>
          <AddressRange Begin=”0” End=”2047”/>
          <Parity ON=”false” NumBits=”0”/>
        </BitLane>
        <BitLane MemType=”RAMB32” Placement=”X4Y14”>
          <DataWidth MSB=”31” LSB=”16”/>
          <AddressRange Begin=”0” End=”2047”/>
          <Parity ON=”false” NumBits=”0”/>
        </BitLane>
      </BusBlock>
    </AddressSpace>
 </Processor>
  <Processor Endianness="Little" InstPath="design_1_i/processing_system7_0">
    <AddressSpace Name="design_1_i_processing_system7_0.design_1_i_axi_bram_ctrl_0" Begin="1073741824" End="1073750015">
      <BusBlock>
        <BitLane MemType="RAMB32" Placement="X2Y18">
          <DataWidth MSB="15" LSB="0"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB32" Placement="X2Y19">
          <DataWidth MSB="31" LSB="16"/>
          <AddressRange Begin="0" End="2047"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
    </AddressSpace>
  </Processor>
  <Config>
    <Option Name="Part" Val="xc7z020clg484-1"/>
  </Config>
</MemInfo>