PCIe Reference Clock

T1 Telco Accelerator Card User Guide (UG1495)
Document ID
UG1495
Release Date
2021-12-17
Revision
1.0 English

The 16 lanes from the PCIe card edge are connected to the Zynq UltraScale+ MPSoC (GTH quads 226 and 227) and the Zynq UltraScale+ RFSoC (GTY quads 130 and 131). Among 16 lanes, x8 are fed to the Zynq UltraScale+ MPSoC and x8 to the Zynq UltraScale+ RFSoC. The PCIe subsystem uses a 100 MHz clock (PCIE_REFCLK).

Table 1. PCIe Reference Clock
Signal Target FPGA Input I/O Standard P Pin N Pin
PCIE_MP_REFCLK MGTREFCLK0_226 HCSL AH10 AH9
PCIE_RF_REFCLK MGTREFCLK0_130 HCSL M28 M29