The Versal ACAP has a heterogeneous processor architecture. The TRD makes use of multiple processing units available inside the CIPS. The APU consists of dual-core Arm Cortex-A72 cores configured to run in SMP Linux mode. The main task of the application is to configure and control the video pipelines as shown in the following figure.
This figure shows the software state after the boot process has completed and the individual applications have been initiated on the target processing units. The TRD does not make use of virtualization and therefore does not run a hypervisor on the APU.
The APU GStreamer application controls the video data paths implemented in a combination of the PS and PL. The following figure depicts the data flow with the following three pipelines:
- Capture pipeline capturing video frames into DDR memory from
- An image sensor on an FMC daughter card connected to the PL (by means of MIPI CSI-2 RX)
- An encoded video file stored in an SD card through the PS SD interface
- Video processing pipeline
- A programmable 2D convolution filter as hardware accelerators in the PL. Video frames are read from DDR memory processed by an accelerator and then written back to memory.
- A soft codec vp9 running on the APU that decodes the file from the SD card and writes it to memory
- A display pipeline reading video frames from memory and sending them to a monitor in the PL (by means of MIPI CSI-2 RX)
The reference design targets the Versal ACAP Prime Series VMK180 evaluation board. The board has an on-board HDMI transmitter and receiver connector. The evaluation board provides the HDMI reference clock, the data recovery unit (DRU) clock, and the reference clock for the design.