When Legacy GT Wizard is used, these ports are part of the ILKNF IP. Otherwise, these pins can be found in the GT Wizard IP as shown in the following figure. The TX and RX interface between ILKNF IP and GT Wizard consist only of data pins.
| Port Name | I/O | Description |
|---|---|---|
| gt_reset_all_in[23:0] | I | Reset input to GT Reset IP. Each bit initiates data path and PLL reset sequence on the corresponding GT lane. Applies to both TX and RX. |
| gt_reset_tx_datapath_in[23:0] | I | Reset input to GT Reset IP. Each bit initiates the TX data path reset sequence on the corresponding GT lane. |
| gt_reset_rx_datapath_in[23:0] | I | Reset input to GT Reset IP. Each bit initiates the RX data path reset sequence on the corresponding GT lane. |
| gt_tx_reset_done_out[23:0] | O | TX Reset Done output from the GT Reset IP. |
| gt_rx_reset_done_out[23:0] | O | RX Reset Done output from the GT Reset IP. |
Figure 1.
ILKNF IP with GT Wizard
Subsystem IP Architecture
Clock and reset connection between ILKNF and GT Wizard IP is shown in the following figure.
Figure 2.
ILKNF and GT Wizard IP Clock
and Reset Architecture
