The DPU control registers are used to
start a DPU core, wait for tasks to complete, and then clear DPU status. The details of
control registers are shown in the following table.
Register | Address Offset | Width | Type | Description |
---|---|---|---|---|
reg_ap_control | 0x000 | 32 | r/w |
|
Global interrupt enable register (GIER) | 0x004 | 32 | r/w |
|
IP interrupt enable register (IPIER) | 0x008 | 32 | r/w |
|
IP interrupt status register (IPISR) | 0x00c | 32 | r/w |
|
reg_dpu_start | 0x010 | 32 | r/w |
|
reg_finish_clr | 0x018 | 32 | r/w |
|
reg_finish_sts | 0x080 | 32 | r |
reg_finish_sts is an asynchronous output that should be trigger a level-sensitive circuit. |