|
Core Specifics |
| Supported Device Family
1
|
UltraScale+™
,
UltraScale™
,
Zynq®-7000 SoC, 7 series
|
| Supported User Interfaces |
JTAG Interface |
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Not Provided |
| Test Bench |
Not Provided |
| Constraints File |
XDC |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
N/A |
| Tested Design Flows |
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change
Logs |
Master Vivado IP Change
Logs: 72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes Guide.
|