The status and statistics registers indicate the health of the link and histograms counters to provide classification of the traffic and error counts. The status and counters are all read-only.
Status registers are cleared on read and counters are controlled by a "tick" mechanism.
Some bits are sticky, that is, latching their values High or Low after being set. This is indicated by the suffix LH (Latched High) or LL (Latched Low).
• R/LL: Register bit defaults to 1, upon error condition this bit latches to 0, the bit is set back to its default state after each read.
• R/LH: Register bit defaults to 0, upon error condition this bit latches to 1, the bit is set back to its default state after each read.
• If the register bit does not default to its respective values after each read, the error state is ongoing.
The counters accumulate their counts in an internal accumulator. A write to the TICK_REG register (or the input port pm_tick is 1'b1) causes the accumulated counts to be pushed to the readable STAT_*_MSB/LSB registers and simultaneously clears the accumulators. The STAT_*_MSB/LSB registers can then be read. In this way all values stored in the statistics counters represent a snapshot over the same time-interval.
The STAT_CYCLE_COUNT_MSB/LSB register contains a count of the number of SerDes clock cycles between TICK_REG register writes. This allows for easy time-interval based statistics. The counters have a default width of 48 bits. The counters saturate to 1s. The values in the counters are held until the next write to the TICK_REG register.
The addresses shown in Table: Status and Statistics Register Map for the counters are the addresses of the LSB register or bits 31:0 of the count. The MSB bits 47:32 of the counter are located at +0x4 from the LSB.
Note: The status and statistics registers should be read after the GT reset is cleared to know the correct live values.
Address |
Register Name |
---|---|
0x0200 |
STAT_TX_STATUS_REG |
0x0204 |
STAT_RX_STATUS_REG |
0x0208 |
STAT_STATUS_REG1 |
0x020C |
STAT_RX_BLOCK_LOCK_REG |
0x0210 |
STAT_RX_LANE_SYNC_REG |
0x0214 |
STAT_RX_LANE_SYNC_ERR_REG |
0x0218 |
STAT_RX_AM_ERR_REG |
0x021C |
STAT_RX_AM_LEN_ERR_REG |
0x0220 |
STAT_RX_AM_REPEAT_ERR_REG |
0x0224 |
STAT_RX_PCSL_DEMUXED_REG |
0x0228 |
STAT_RX_PCS_LANE_NUM_REG1 |
0x022C |
STAT_RX_PCS_LANE_NUM_REG2 |
0x0230 |
STAT_RX_PCS_LANE_NUM_REG3 |
0x0234 |
STAT_RX_PCS_LANE_NUM_REG4 |
0x0238 |
STAT_RX_BIP_OVERRIDE_REG |
0x023C–0x0254 |
Reserved |
0x0258 |
STAT_AN_STATUS_REG |
0x025C |
STAT_AN_ABILITY_REG |
0x0260 |
STAT_AN_LINK_CTL_REG_1 |
0x0264 |
STAT_LT_STATUS_REG1 |
0x0268 |
STAT_LT_STATUS_REG2 |
0x026C |
STAT_LT_STATUS_REG3 |
0x0270 |
STAT_LT_STATUS_REG4 |
0x0274 |
STAT_LT_COEFFICIENT0_REG |
0x0278 |
STAT_LT_COEFFICIENT1_REG |
0x027C |
STAT_AN_LINK_CTL_REG_2 |
0x0280–0x02AF |
Reserved |
Histogram/Counter Registers (1) |
|
0x02B0 |
TICK_REG |
0x02B8 |
STAT_CYCLE_COUNT |
0x02C0 |
STAT_RX_BIP_ERR_0 |
0x02C8 |
STAT_RX_BIP_ERR_1 |
0x02D0 |
STAT_RX_BIP_ERR_2 |
0x02D8 |
STAT_RX_BIP_ERR_3 |
0x02E0 |
STAT_RX_BIP_ERR_4 |
0x02E8 |
STAT_RX_BIP_ERR_5 |
0x02F0 |
STAT_RX_BIP_ERR_6 |
0x02F8 |
STAT_RX_BIP_ERR_7 |
0x0300 |
STAT_RX_BIP_ERR_8 |
0x0308 |
STAT_RX_BIP_ERR_9 |
0x0310 |
STAT_RX_BIP_ERR_10 |
0x0318 |
STAT_RX_BIP_ERR_11 |
0x0320 |
STAT_RX_BIP_ERR_12 |
0x0328 |
STAT_RX_BIP_ERR_13 |
0x0330 |
STAT_RX_BIP_ERR_14 |
0x0338 |
STAT_RX_BIP_ERR_15 |
0x0340 |
STAT_RX_BIP_ERR_16 |
0x0348 |
STAT_RX_BIP_ERR_17 |
0x0350 |
STAT_RX_BIP_ERR_18 |
0x0358 |
STAT_RX_BIP_ERR_19 |
0x0360 |
STAT_RX_FRAMING_ERR_0 |
0x0368 |
STAT_RX_FRAMING_ERR_1 |
0x0370 |
STAT_RX_FRAMING_ERR_2 |
0x0378 |
STAT_RX_FRAMING_ERR_3 |
0x0380 |
STAT_RX_FRAMING_ERR_4 |
0x0388 |
STAT_RX_FRAMING_ERR_5 |
0x0390 |
STAT_RX_FRAMING_ERR_6 |
0x0398 |
STAT_RX_FRAMING_ERR_7 |
0x03A0 |
STAT_RX_FRAMING_ERR_8 |
0x03A8 |
STAT_RX_FRAMING_ERR_9 |
0x03B0 |
STAT_RX_FRAMING_ERR_10 |
0x03B8 |
STAT_RX_FRAMING_ERR_11 |
0x03C0 |
STAT_RX_FRAMING_ERR_12 |
0x03C8 |
STAT_RX_FRAMING_ERR_13 |
0x03D0 |
STAT_RX_FRAMING_ERR_14 |
0x03D8 |
STAT_RX_FRAMING_ERR_15 |
0x03E0 |
STAT_RX_FRAMING_ERR_16 |
0x03E8 |
STAT_RX_FRAMING_ERR_17 |
0x03F0 |
STAT_RX_FRAMING_ERR_18 |
0x03F8 |
STAT_RX_FRAMING_ERR_19 |
0x0400–0x0410 |
Reserved |
0x0418 |
STAT_RX_BAD_CODE |
0x0420 |
Reserved |
0x0428 |
Reserved |
0x0430 |
Reserved |
0x0438 |
Reserved |
0x0440 |
Reserved |
0x0448 |
Reserved |
0x0450 |
Reserved |
0x0458 |
STAT_TX_FRAME_ERROR |
0x0460 |
Reserved |
0x0500 |
STAT_TX_TOTAL_PACKETS |
0x0508 |
STAT_TX_TOTAL_GOOD_PACKETS |
0x0510 |
STAT_TX_TOTAL_BYTES |
0x0518 |
STAT_TX_TOTAL_GOOD_BYTES |
0x0520 |
STAT_TX_PACKET_64_BYTES |
0x0528 |
STAT_TX_PACKET_65_127_BYTES |
0x0530 |
STAT_TX_PACKET_128_255_BYTES |
0x0538 |
STAT_TX_PACKET_256_511_BYTES |
0x0540 |
STAT_TX_PACKET_512_1023_BYTES |
0x0548 |
STAT_TX_PACKET_1024_1518_BYTES |
0x0550 |
STAT_TX_PACKET_1519_1522_BYTES |
0x0558 |
STAT_TX_PACKET_1523_1548_BYTES |
0x0560 |
STAT_TX_PACKET_1549_2047_BYTES |
0x0568 |
STAT_TX_PACKET_2048_4095_BYTES |
0x0570 |
STAT_TX_PACKET_4096_8191_BYTES |
0x0578 |
STAT_TX_PACKET_8192_9215_BYTES |
0x0580 |
STAT_TX_PACKET_LARGE |
0x0588 |
STAT_TX_PACKET_SMALL |
0x0590–0x05B0 |
Reserved |
0x05B8 |
STAT_TX_BAD_FCS |
0x05C0 |
Reserved |
0x05C8 |
Reserved |
0x05D0 |
STAT_TX_UNICAST |
0x05D8 |
STAT_TX_MULTICAST |
0x05E0 |
STAT_TX_BROADCAST |
0x05E8 |
STAT_TX_VLAN |
0x05F0 |
STAT_TX_PAUSE |
0x05F8 |
STAT_TX_USER_PAUSE |
0x0600 |
Reserved |
0x0608 |
STAT_RX_TOTAL_PACKETS |
0x0610 |
STAT_RX_TOTAL_GOOD_PACKETS |
0x0618 |
STAT_RX_TOTAL_BYTES |
0x0620 |
STAT_RX_TOTAL_GOOD_BYTES |
0x0628 |
STAT_RX_PACKET_64_BYTES |
0x0630 |
STAT_RX_PACKET_65_127_BYTES |
0x0638 |
STAT_RX_PACKET_128_255_BYTES |
0x0640 |
STAT_RX_PACKET_256_511_BYTES |
0x0648 |
STAT_RX_PACKET_512_1023_BYTES |
0x0650 |
STAT_RX_PACKET_1024_1518_BYTES |
0x0658 |
STAT_RX_PACKET_1519_1522_BYTES |
0x0660 |
STAT_RX_PACKET_1523_1548_BYTES |
0x0668 |
STAT_RX_PACKET_1549_2047_BYTES |
0x0670 |
STAT_RX_PACKET_2048_4095_BYTES |
0x0678 |
STAT_RX_PACKET_4096_8191_BYTES |
0x0680 |
STAT_RX_PACKET_8192_9215_BYTES |
0x0688 |
STAT_RX_PACKET_LARGE |
0x0690 |
STAT_RX_PACKET_SMALL |
0x0698 |
STAT_RX_UNDERSIZE |
0x06A0 |
STAT_RX_FRAGMENT |
0x06A8 |
STAT_RX_OVERSIZE |
0x06B0 |
STAT_RX_TOOLONG |
0x06B8 |
STAT_RX_JABBER |
0x06C0 |
STAT_RX_BAD_FCS |
0x06C8 |
STAT_RX_PACKET_BAD_FCS |
0x06D0 |
STAT_RX_STOMPED_FCS |
0x06D8 |
STAT_RX_UNICAST |
0x06E0 |
STAT_RX_MULTICAST |
0x06E8 |
STAT_RX_BROADCAST |
0x06F0 |
STAT_RX_VLAN |
0x06F8 |
STAT_RX_PAUSE |
0x0700 |
STAT_RX_USER_PAUSE |
0x0708 |
STAT_RX_INRANGEERR |
0x0710 |
STAT_RX_TRUNCATED |
0x0718–0x07FF |
Reserved |
Notes: 1. Histogram/Counter registers are available when Include Statistics Counters option is selected in This Figure . |