IP Facts - 1.2 English

ThunderBus IP (PB075)

Document ID
Release Date
1.2 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family UltraScale+™

Kintex® UltraScale™

Virtex® UltraScale™

Versal® ACAP

Supported User Interfaces AXI4-Stream


Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Source HDL with SecureIP transceiver simulation models
Supported S/W Driver N/A
Tested Design Flows 1
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Design Suite
Release Notes and Known Issues Master Answer Record: N/A
Xilinx Support web page
  1. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.