| LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family |
UltraScale+™
Kintex® UltraScale™ Virtex® UltraScale™ Versal® ACAP |
| Supported User Interfaces |
AXI4-Stream
AXI4 |
| Provided with Core | |
| Design Files | Encrypted RTL |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Source HDL with SecureIP transceiver simulation models |
| Supported S/W Driver | N/A |
| Tested Design Flows 1 | |
| Design Entry | Vivado® Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Vivado Design Suite |
| Support | |
| Release Notes and Known Issues | Master Answer Record: N/A |
| Xilinx Support web page | |
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