Core Specifics |
Supported Device Family
1
|
Versal Adaptive SoC,
AMD UltraScale™
, AMD UltraScale+™
2
|
Supported User Interfaces |
N/A |
Resources |
Performance and Resource
Utilization web page
|
Provided with Core
|
Design Files |
Encrypted RTL |
Example Design |
N/A |
Test Bench |
Not Provided |
Constraints File |
Xilinx Constraints File (XDC) |
Simulation Model |
Encrypted Verilog |
Supported S/W Driver |
N/A |
Tested Design Flows
3
|
Design Entry |
AMD Vivado™ Design Suite
|
Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
Synthesis |
AMD Vivado™ Design Suite
|
Support |
Release Notes and Known Issues |
Master Answer Record: 73658
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
Support web
page
|
- For a complete list of supported devices, see
the AMD Vivado™
IP catalog.
- -1 speed grades are not supported for these
devices.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|