The DSP slices in the computation unit module are in the dpu_2x_clk
domain, which runs at twice the clock frequency of the data controller module. The two
related clocks must be edge-aligned.
The DSP slices in the computation unit module are in the dpu_2x_clk
domain, which runs at twice the clock frequency of the data controller module. The two
related clocks must be edge-aligned.