| Command/Property Name | Description |
|---|---|
| HD.CLK_SRC | Used in the OOC implementation to tell the implementation tools if a
clock buffer will be used outside of the out-of-context module. The
value is the location of the clock buffer instance. This is applied
on a clock port, and the port must have a clock defined
(create_clock) prior to this constraint being
applied. |
| HD.PARTPIN_LOCS | Defines a specific interconnect tile (INT) for the specified port to be routed.
Overrides an HD.PARTPIN_RANGE value. Affects placement and routing
of internal OOC logic. Do not use on clock ports because this assumes local routing for the clock. Do not use on dedicated connections. |
| HD.PARTPIN_RANGE | Defines a range of component sites (SLICE, DSP, block RAM) or interconnect tiles (INT)
that can be used to route the specified pin(s)/port(s). This constraint is only valid for pins or ports that are do not have dedicated connections (for example, clocks or direct connections to top-level I/O pads). If applied to these pins or ports, the constraint is ignored. |
| set_logic_unconnected | Allows for additional optimization for any specified output ports that will be left unconnected in Top. |
| set_logic_one | Allows for additional optimization for any specified input ports that are driven by VCC in Top. |
| set_logic_zero | Allows for additional optimization for any specified input ports that are driven by GND in Top. |
ERROR:[Opt 31-67] Problem: A LUT2 cell in the design is
missing a connection on input pin I0, which is used by the LUT
equation.Context Constraint Examples
-
set_property HD.CLK_SRC BUFGCTRL_X0Y16 [get_ports <port_name>] -
set_property HD.PARTPIN_LOCS INT_R_X0Y0 [get_ports <port_name>] -
set_property HD.PARTPIN_RANGE SLICE_X0Y1:SLICE_X1Y3 [get_ports <port_name>] -
set_logic_unconnected [get_ports <port_name>] -
set_logic_one [get_ports <port_name>] -
set_logic_zero [get_ports <port_name>]
By default, in the Module Analysis flow, interface nets (nets inside the
module connected to the OOC module ports) are not routed. To have these interface
nets routed, you must lock the module ports using HD.PARTPIN constraints. To get a
quick placement of module ports (or partition pins), the HD.PARTPIN_RANGE can be
used with a value of the OOC module Pblock SLICE range. To obtain more specific
placement of these pins, tighter HD.PARTPIN_RANGE values can be used, or explicit
HD.PARTPIN_LOCS values can be specified. To determine what an appropriate site or
range might be, open the Device View in the Vivado IDE and enable Routing Resources by clicking this button: 
.
When you zoom in, you see INT locations as shown in the following figure (routing resources are hidden to simplify this image):
