Vitis Model Composer automates the flow of generating the
hardware image out of a design containing AI Engine, HDL, and HLS kernel blocks. These
steps differ slightly based on the communication among the AI Engine and different
Programmable Logic (HLS kernel or HDL) blocks. This section provides details for
generating a hardware image for:
- A design with AI Engine and HLS kernel blocks.
- A design with AI Engine and HDL blocks.