Getting Started with Vitis Revision History
The following table shows the revision history for Getting Started with Vitis.
| Section | Revision Summary |
|---|---|
| 12/15/2020 Version 2020.2 | |
| N/A | No updates to this section. |
| 11/24/2020 Version 2020.2 | |
| Vitis Software Platform Installation | Updated content. |
| 06/24/2020 Version 2020.1 | |
| Vitis Software Platform Installation | Added information about using XRT on Ubuntu. |
| 06/03/2020 Version 2020.1 | |
| Vitis Software Platform Release Notes | Updated content. |
| Comparing Workflows in the Vitis Software Platform and SDK | Updated workflow comparison. |
| 03/18/2020 Version 2019.2 | |
| N/A | Minor editorial updates. |
| 02/28/2020 Version 2019.2 | |
| N/A | Minor editorial updates. |
| N/A | Minor editorial updates. |
| 11/11/2019 Version 2019.212/18/2019 Version 2019.2 | |
| Vitis Software Platform Release Notes | Updated content. |
| Installation Requirements | Updated content and removed licensing information. |
| Vitis Software Platform Installation | Updated content. |
| 10/30/2019 Version 2019.2 | |
| Initial release. | N/A |
Using the Vitis IDE Revision History
The following table shows the revision history for Using the Vitis IDE.
| Section | Revision Summary |
|---|---|
| 12/15/2020 Version 2020.2 | |
| Creating a Platform Project from XSA | Updated instructions. |
| Target Platform | Minor clarifications. |
| Adding a Standalone Domain | Updated instructions. |
| Adding a Linux Domain | Updated instructions. |
| Adding a FreeRTOS Domain | Updated instructions. |
| Configuring a Domain | Revised content about configuration options. |
| 11/24/2020 Version 2020.2 | |
| Program Device | Updated information. |
| Cross-Triggering in Versal Devices | Added new section. |
| Exporting Registers from the Vitis IDE | New feature. |
| Version Control with Git | New information about Git integration. |
| 06/24/2020 Version 2020.1 | |
| General | No content updates in this section. |
| 06/03/2020 Version 2020.1 | |
| Target Platform | Updated flows in this section for 2020.1. |
| Applications | Updated flows in this section for 2020.1. |
| Run, Debug, and Optimize | Updated flows in this section for 2020.1. |
| User Makefile Flow | Added new information about the user Makefile flow. |
| Using the Standalone Debug Flow | New section. |
| 03/18/2020 Version 2019.2 | |
| BSP, DTS, and Application Generation in Vivado | Removed section |
| 02/28/2020 Version 2019.2 | |
| FreeRTOS Analysis using STM | Updated flow. |
| TCF Profiling | Updated flow. |
| System Performance Modeling Using a User-Defined Flow | Updated flow. |
| 12/18/2019 Version 2019.2 | |
| Creating a Platform Project from XSA | Corrected flow. |
| Migrating an SDK Project to the Vitis Software Platform | Added new use case. |
| 11/11/2019 Version 2019.2 | |
| N/A | Minor editorial updates. |
| 10/30/2019 Version 2019.2 | |
| Initial release. | N/A |
Bootgen Revision History
The following table shows the revision history for Bootgen Tool.
| Section | Revision Summary |
|---|---|
| 12/15/2020 Version 2020.2 | |
| Versal Authentication Support | Minor clarification. |
| 11/24/2020 Version 2020.2 | |
| General updates | Gray/obfuscated keys are deprecated for Versal™ devices. |
| authenticatedjtag | The authenticatedjtag command replaces securedebugimage. |
| Creating a Versal Device Boot Image using HSM | Added new section. |
| a_hwrot and s_hwrot | New attributes. |
| General updates | New BIF code examples added throughout. |
| Appending New Partitions to Existing PDI | Steps updated. |
| Replacing PLM from an Existing PDI | Steps updated. |
| 06/03/2020 Version 2020.1 | |
| General updates | Minor editorial changes. |
| NIST SHA-3 Support | Updated the Authentication Signatures tables. |
| Creating a Zynq-7000 SoC Device Boot Image using HSM Mode | Updated section. |
| Split with "Offset" Attribute | Added new section. |
| aeskeyfile | Updated section. |
| 10/30/2019 Version 2019.2 | |
| General updates | Minor editorial changes. |
| Chapter 2 | Added Zynq UltraScale+ MPSoC Secure Header |
| Chapter 5 | Updated Creating a Zynq-7000 SoC Device Boot Image using HSM Mode. |
| Appendix B | Added attributes: |
| Appendix C | Added command verify_kdf |
| Using HSM Mode | Added PPK inputs to Stage 0 elements |
| 05/22/2019 Version 2019.1 | |
| General updates | Minor editorial changes. |
Xilinx Software Command-Line Tool Revision History
The following table shows the revision history for Xilinx Software Command-Line Tool.
| Section | Revision Summary |
|---|---|
| 12/15/2020 Version 2020.2 | |
| N/A | No updates to this section. |
| 11/24/2020 Version 2020.2 | |
| XSCT Commands | Updated commands list for 2020.2. |
| 06/03/2020 Version 2020.1 | |
| General Updates | This release is focused on updating the document for use with Vitis™ Integrated Development Environment. |
| XSCT Use Cases | Added new sections: Exchanging Files between Host Machine and Linux running on QEMU and Creating an FSBL Application Project Using Manually Created Domain (Zynq UltraScale+ MPSoC FSBL). |
| 03/19/2020 Version 2019.2 | |
| General Updates | This release is focused on updating the document for use with Vitis™ Integrated Development Environment. |
| Hardware Software Interface (HSI) Commands | Added new section. |
| 05/22/2019 Version 2019.1 | |
| General Updates | This release is focused on quality. A number of quality related issues and bug fixes were addressed in this release. |