- From the Vivado IDE Getting Started page,
select to create a new project.
Tip: You can use either an RTL project or a Manage IP project to validate IP. - Click Next in the New IP Location dialog box.
- In the Manage IP Settings dialog box, set the following options as they
appear in the following figure.
- Part
- xc7k325tffg900-2
- Target language
- Verilog
- Target Simulator
- Vivado simulator
- Simulator Language
- Mixed
- IP Location
- <Extract_Dir>/lab_1
- Click Finish to create the Manage IP
project.
A new Manage IP project opens in the Vivado IDE. The IP catalog opens automatically in a Manage IP project; however, the IP Catalog does not contain the repository used to package the custom UART IP.
You now add the IP repository to the IP catalog.
- In the IP Catalog window, right-click and select IP Settings, and expand IP to show Repository.
- In the Repository Manager tab, click the Add Repository button to show and then select the IP Repositories Dialog Box.
- In the IP Repositories dialog box, browse to and select the following
location:
<Extract_Dir>/my_simple_uart.srcs/
- Click Select to add the selected
repository, as shown in the following figure:
The added location displays in the IP Repositories section, and any packaged IP found in the repositories displays under the IP in Selected Repository. The My Simple UART IP definition that you packaged in Step 3: Package the IP is listed.
- Click OK twice to add the IP
repository to the IP Catalog and close the dialog box.Tip: To define a custom IP repository for use across multiple design projects, you can use the command in the Vivado IDE to set the Default IP Repository Search Paths under the General IP options. The default IP repository search path is stored in the vivado.xml file, and added to new projects using the IP_REPO_PATHS property for the current_fileset :
set_property IP_REPO_PATHS {…} [current_fileset]
. (See the Vivado Design Suite Properties Reference Guide (UG912) for more information.) - In the search field at the top of the IP Catalog, type
UART
.The My Simple UART is reported under the UserIP and Serial Interfaces categories that it was previously assigned to during packaging, as shown in the following figure.
Note: This IP Catalog view shows when the Taxonomy and the Repository options are selected for grouping the IP. See the Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118) for more information about IP Groups. - Select the My Simple UART by clicking it under either the UserIP or Serial Interfaces category.
- Examine the Details pane of the IP Catalog window, as shown in the following
figure.
Notice that the details match the information provided when you packaged the IP.
- In the IP catalog, double-click My Simple
UART to open the Customize IP dialog box, shown in the following
figure.
- (Optional) In the Customize IP dialog box, click Documentation and open the Product Guide.
- Click OK, accepting the default
Component Name and other options.
The Vivado packager adds the customized IP to the current project, and displays the IP in the IP Sources window.
The Generate Output Products dialog box opens, as shown in the following figure.
- Click Generate.
This generates the various files required for this IP in the current Manage IP project, and launches an out-of-context (OOC) synthesis run for the IP, which creates a design checkpoint (DCP) file.
Recall this OOC synthesis run uses the OOC XDC file that defines the necessary clocks for the standalone IP.
The Generate Output Products dialog box re-opens to report the output products generated successfully.
- Click OK.
- Examine the IP Sources window and the various design and simulation source files that are added to the project.
- In the Design Runs window, shown in the following figure, verify that the
Out-Of-Context synthesis run was successful.
With the new custom IP definition
packaged and added to the IP Catalog, you can validate that the IP works as expected
when added to designs. To validate the IP, add a new customization of the UART IP to a
project, and synthesize the design.