Resets - 2.3 English

Binary CAM Search LogiCORE IP Product Guide (PG317)

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2.3 English

At startup, both the AXI reset and the main reset must be asserted simultaneously for four cycles of the slower of the two clocks (s_axi_aclk and key_clk). As long as the reset assertion time is met, either reset can be asserted or negated first. The system is not ready to use until the reset phase is finished (indicated by the rst_busy output). The rst_busy output is high for approximately 30 clock cycles (slowest clock).