To meet the debug objectives and to accomplish use cases, Versal™ device has an inbuilt, flexible, and high speed debug subsystem called high speed debug port (HSDP). HSDP is similar to and replacement of ARM-DAP in Versal device. Though HSDP has many sub blocks and distributed into many domains of Versal platform but can be defined for simplicity as a combination of DPC and four different host interfaces. The four host interfaces are available in Versal device as part of HSDP subsystem are:
- JTAG - Bridge in PMC
- Hard Aurora in PS
- CPM4 PCIe Controller
- Soft Aurora in PL fabric
- Ingress AXI-S
- A slave AXI-S port where command packets arrive from/through
these sources/paths.
- JTAG PMC_TAP BSCAN Bridge
- GT CPM4 XPIPE Aurora Wrapper
- GT CPM4 PCIe Controller Ingress DMA
- Soft Aurora in PL Fabric
- Egress AXI-S
- A master AXI-S port where reply packets depart through/to
these paths/destinations.
- BSCAN Bridge ->PMC_TAP -> JTAG
- Aurora Wrapper -> CPM4 XPIPE -> GT
- Egress DMA ->CPM4 PCIe Controller -> GT
- Soft Aurora in PL Fabric
The major datapath of the HSDP is AXI-S. All other types of signaling JTAG, Gigabit (GT), PCIe, AXI-4, XPIPE etc. are converted into AXI-S by conversion blocks including BSCAN Bridge, Ingress DMA, and Egress DMA. Wherever clock domain crossing is necessary, an AXI-S Async Bridge is employed, and wherever 2 AXI-S buses meet, a mux and demux are used.
