Core Specifics |
Supported Device Family
1
|
Kintex®
UltraScale™
,
Virtex®
UltraScale™
,
Zynq®-7000 SoC,
Kintex®
UltraScale+™
,
Virtex®
UltraScale+™
,
Zynq®
UltraScale+™ MPSoC,
Zynq®
UltraScale+™ RFSoC,
Versal™
ACAP. |
Supported User Interfaces |
AXI4-Stream
|
Resources |
Performance and Resource Use web
page (registration required) |
Provided with Core
|
Design Files |
Encrypted RTL |
Example Design |
Verilog |
Test Bench |
Verilog |
Constraints File |
Xilinx Design Constraints (XDC) |
Simulation Model |
Verilog |
Supported S/W Driver |
Linux user space driver (Libmetal) |
Tested Design Flows
2
|
Design Entry |
Vivado® Design Suite
|
Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known
Issues |
Master Answer Record:
73648
|
All Vivado IP
Change Logs |
Master Vivado IP
Change Logs: 72775
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|