The DPU configuration registers are used to indicate instruction address, common address and mean value settings.

The `reg_instr_addr`

register is used to indicate the
instruction address of all DPU processing engines.

The reg_base_addr register is used to indicate the address of input image and parameters for the DPU in external memory. The width of a DPU base address is 44 bits. All registers are 32 bits wide, so two registers are required to represent a 44-bit wide base address. reg_dpu0_base_addr0_l represents the lower 32 bits of base_address0 in DPU batch 0 and reg_dpu0_base_addr0_h represents the upper 12 bits of base_address0 in DPU batch 0.

There are eight groups of DPU base addresses for each DPU batch engine and thus 64 groups of DPU base addresses for up to eight DPU batch engines.

The details of configuration registers are shown in the following table:

Register | Address Offset | Width | Type | Description |
---|---|---|---|---|

reg_instr_addr_l | 0x140 | 32 | r/w | The lower 32 bits of instruction address of DPU. 4 KB aligned. |

reg_instr_addr_h | 0x144 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of instruction address of DPU. 4 KB aligned. |

reg_engine0_base_addr_0_l | 0x100 | 32 | r/w | The lower 32 bits of base address0 of DPU engine0. |

reg_engine0_base_addr_0_h | 0x104 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine0. |

reg_engine0_base_addr_1_l | 0x108 | 32 | r/w | The lower 32 bits of base address1 of DPU engine0. |

reg_engine0_base_addr_1_h | 0x10c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine0. |

reg_engine0_base_addr_2_l | 0x110 | 32 | r/w | The lower 32 bits of base address2 of DPU engine0. |

reg_engine0_base_addr_2_h | 0x114 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine0. |

reg_engine0_base_addr_3_l | 0x118 | 32 | r/w | The lower 32 bits of base address3 of DPU engine0. |

reg_engine0_base_addr_3_h | 0x11c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine0. |

reg_engine0_base_addr_4_l | 0x120 | 32 | r/w | The lower 32 bits of base address4 of DPU engine0. |

reg_engine0_base_addr_4_h | 0x124 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine0. |

reg_engine0_base_addr_5_l | 0x128 | 32 | r/w | The lower 32 bits of base address5 of DPU engine0. |

reg_engine0_base_addr_5_h | 0x12c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine0. |

reg_engine0_base_addr_6_l | 0x130 | 32 | r/w | The lower 32 bits of base address6 of DPU engine0. |

reg_engine0_base_addr_6_h | 0x134 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine0. |

reg_engine0_base_addr_7_l | 0x138 | 32 | r/w | The lower 32 bits of base address7 of DPU engine0. |

reg_engine0_base_addr_7_h | 0x13c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine0. |

reg_engine1_base_addr_0_l | 0x200 | 32 | r/w | The lower 32 bits of base address0 of DPU engine1. |

reg_engine1_base_addr_0_h | 0x204 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine1. |

reg_engine1_base_addr_1_l | 0x208 | 32 | r/w | The lower 32 bits of base address1 of DPU engine1. |

reg_engine1_base_addr_1_h | 0x20c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine1. |

reg_engine1_base_addr_2_l | 0x210 | 32 | r/w | The lower 32 bits of base address2 of DPU engine1. |

reg_engine1_base_addr_2_h | 0x214 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine1. |

reg_engine1_base_addr_3_l | 0x218 | 32 | r/w | The lower 32 bits of base address3 of DPU engine1. |

reg_engine1_base_addr_3_h | 0x21c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine1. |

reg_engine1_base_addr_4_l | 0x220 | 32 | r/w | The lower 32 bits of base address4 of DPU engine1. |

reg_engine1_base_addr_4_h | 0x224 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine1. |

reg_engine1_base_addr_5_l | 0x228 | 32 | r/w | The lower 32 bits of base address5 of DPU engine1. |

reg_engine1_base_addr_5_h | 0x22c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine1. |

reg_engine1_base_addr_6_l | 0x230 | 32 | r/w | The lower 32 bits of base address6 of DPU engine1. |

reg_engine1_base_addr_6_h | 0x234 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine1. |

reg_engine1_base_addr_7_l | 0x238 | 32 | r/w | The lower 32 bits of base address7 of DPU engine1. |

reg_engine1_base_addr_7_h | 0x23c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine1. |

reg_engine2_base_addr_0_l | 0x300 | 32 | r/w | The lower 32 bits of base address0 of DPU engine2. |

reg_engine2_base_addr_0_h | 0x304 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine2. |

reg_engine2_base_addr_1_l | 0x308 | 32 | r/w | The lower 32 bits of base address1 of DPU engine2. |

reg_engine2_base_addr_1_h | 0x30c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine2. |

reg_engine2_base_addr_2_l | 0x310 | 32 | r/w | The lower 32 bits of base address2 of DPU engine2. |

reg_engine2_base_addr_2_h | 0x314 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine2. |

reg_engine2_base_addr_3_l | 0x318 | 32 | r/w | The lower 32 bits of base address3 of DPU engine2. |

reg_engine2_base_addr_3_h | 0x31c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine2. |

reg_engine2_base_addr_4_l | 0x320 | 32 | r/w | The lower 32 bits of base address4 of DPU engine2. |

reg_engine2_base_addr_4_h | 0x324 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine2. |

reg_engine2_base_addr_5_l | 0x328 | 32 | r/w | The lower 32 bits of base address5 of DPU engine2. |

reg_engine2_base_addr_5_h | 0x32c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine2. |

reg_engine2_base_addr_6_l | 0x330 | 32 | r/w | The lower 32 bits of base address6 of DPU engine2. |

reg_engine2_base_addr_6_h | 0x334 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine2. |

reg_engine2_base_addr_7_l | 0x338 | 32 | r/w | The lower 32 bits of base address7 of DPU engine2. |

reg_engine2_base_addr_7_h | 0x33c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine2. |

reg_engine3_base_addr_0_l | 0x400 | 32 | r/w | The lower 32 bits of base address0 of DPU engine3. |

reg_engine3_base_addr_0_h | 0x404 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine3. |

reg_engine3_base_addr_1_l | 0x408 | 32 | r/w | The lower 32 bits of base address1 of DPU engine3. |

reg_engine3_base_addr_1_h | 0x40c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine3. |

reg_engine3_base_addr_2_l | 0x410 | 32 | r/w | The lower 32 bits of base address2 of DPU engine3. |

reg_engine3_base_addr_2_h | 0x414 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine3. |

reg_engine3_base_addr_3_l | 0x418 | 32 | r/w | The lower 32 bits of base address3 of DPU engine3. |

reg_engine3_base_addr_3_h | 0x41c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine3. |

reg_engine3_base_addr_4_l | 0x420 | 32 | r/w | The lower 32 bits of base address4 of DPU engine3. |

reg_engine3_base_addr_4_h | 0x424 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine3. |

reg_engine3_base_addr_5_l | 0x428 | 32 | r/w | The lower 32 bits of base address5 of DPU engine3. |

reg_engine3_base_addr_5_h | 0x42c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine3. |

reg_engine3_base_addr_6_l | 0x430 | 32 | r/w | The lower 32 bits of base address6 of DPU engine3. |

reg_engine3_base_addr_6_h | 0x434 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine3. |

reg_engine3_base_addr_7_l | 0x438 | 32 | r/w | The lower 32 bits of base address7 of DPU engine3. |

reg_engine3_base_addr_7_h | 0x43c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine3. |

reg_engine4_base_addr_0_l | 0x500 | 32 | r/w | The lower 32 bits of base address0 of DPU engine4. |

reg_engine4_base_addr_0_h | 0x504 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine4. |

reg_engine4_base_addr_1_l | 0x508 | 32 | r/w | The lower 32 bits of base address1 of DPU engine4. |

reg_engine4_base_addr_1_h | 0x50c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine4. |

reg_engine4_base_addr_2_l | 0x510 | 32 | r/w | The lower 32 bits of base address2 of DPU engine4. |

reg_engine4_base_addr_2_h | 0x514 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine4. |

reg_engine4_base_addr_3_l | 0x518 | 32 | r/w | The lower 32 bits of base address3 of DPU engine4. |

reg_engine4_base_addr_3_h | 0x51c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine4. |

reg_engine4_base_addr_4_l | 0x520 | 32 | r/w | The lower 32 bits of base address4 of DPU engine4. |

reg_engine4_base_addr_4_h | 0x524 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine4. |

reg_engine4_base_addr_5_l | 0x528 | 32 | r/w | The lower 32 bits of base address5 of DPU engine4. |

reg_engine4_base_addr_5_h | 0x52c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine4. |

reg_engine4_base_addr_6_l | 0x530 | 32 | r/w | The lower 32 bits of base address6 of DPU engine4. |

reg_engine4_base_addr_6_h | 0x534 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine4. |

reg_engine4_base_addr_7_l | 0x538 | 32 | r/w | The lower 32 bits of base address7 of DPU engine4. |

reg_engine4_base_addr_7_h | 0x53c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine4. |

reg_engine5_base_addr_0_l | 0x600 | 32 | r/w | The lower 32 bits of base address0 of DPU engine5. |

reg_engine5_base_addr_0_h | 0x604 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine5. |

reg_engine5_base_addr_1_l | 0x608 | 32 | r/w | The lower 32 bits of base address1 of DPU engine5. |

reg_engine5_base_addr_1_h | 0x60c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine5. |

reg_engine5_base_addr_2_l | 0x610 | 32 | r/w | The lower 32 bits of base address2 of DPU engine5. |

reg_engine5_base_addr_2_h | 0x614 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine5. |

reg_engine5_base_addr_3_l | 0x618 | 32 | r/w | The lower 32 bits of base address3 of DPU engine5. |

reg_engine5_base_addr_3_h | 0x61c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine5. |

reg_engine5_base_addr_4_l | 0x620 | 32 | r/w | The lower 32 bits of base address4 of DPU engine5. |

reg_engine5_base_addr_4_h | 0x624 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine5. |

reg_engine5_base_addr_5_l | 0x628 | 32 | r/w | The lower 32 bits of base address5 of DPU engine5. |

reg_engine5_base_addr_5_h | 0x62c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine5. |

reg_engine5_base_addr_6_l | 0x630 | 32 | r/w | The lower 32 bits of base address6 of DPU engine5. |

reg_engine5_base_addr_6_h | 0x634 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine5. |

reg_engine5_base_addr_7_l | 0x638 | 32 | r/w | The lower 32 bits of base address7 of DPU engine5. |

reg_engine5_base_addr_7_h | 0x63c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine5. |

reg_engine6_base_addr_0_l | 0x700 | 32 | r/w | The lower 32 bits of base address0 of DPU engine6. |

reg_engine6_base_addr_0_h | 0x704 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine6. |

reg_engine6_base_addr_1_l | 0x708 | 32 | r/w | The lower 32 bits of base address1 of DPU engine6. |

reg_engine6_base_addr_1_h | 0x70c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine6. |

reg_engine6_base_addr_2_l | 0x710 | 32 | r/w | The lower 32 bits of base address2 of DPU engine6. |

reg_engine6_base_addr_2_h | 0x714 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine6. |

reg_engine6_base_addr_3_l | 0x718 | 32 | r/w | The lower 32 bits of base address3 of DPU engine6. |

reg_engine6_base_addr_3_h | 0x71c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine6. |

reg_engine6_base_addr_4_l | 0x720 | 32 | r/w | The lower 32 bits of base address4 of DPU engine6. |

reg_engine6_base_addr_4_h | 0x724 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine6. |

reg_engine6_base_addr_5_l | 0x728 | 32 | r/w | The lower 32 bits of base address5 of DPU engine6. |

reg_engine6_base_addr_5_h | 0x72c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine6. |

reg_engine6_base_addr_6_l | 0x730 | 32 | r/w | The lower 32 bits of base address6 of DPU engine6. |

reg_engine6_base_addr_6_h | 0x734 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine6. |

reg_engine6_base_addr_7_l | 0x738 | 32 | r/w | The lower 32 bits of base address7 of DPU engine6. |

reg_engine6_base_addr_7_h | 0x73c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine6. |

reg_engine7_base_addr_0_l | 0x800 | 32 | r/w | The lower 32 bits of base address0 of DPU engine7. |

reg_engine7_base_addr_0_h | 0x804 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address0 of DPU engine7. |

reg_engine7_base_addr_1_l | 0x808 | 32 | r/w | The lower 32 bits of base address1 of DPU engine7. |

reg_engine7_base_addr_1_h | 0x80c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address1 of DPU engine7. |

reg_engine7_base_addr_2_l | 0x810 | 32 | r/w | The lower 32 bits of base address2 of DPU engine7. |

reg_engine7_base_addr_2_h | 0x814 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address2 of DPU engine7. |

reg_engine7_base_addr_3_l | 0x818 | 32 | r/w | The lower 32 bits of base address3 of DPU engine7. |

reg_engine7_base_addr_3_h | 0x81c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address3 of DPU engine7. |

reg_engine7_base_addr_4_l | 0x820 | 32 | r/w | The lower 32 bits of base address4 of DPU engine7. |

reg_engine7_base_addr_4_h | 0x824 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address4 of DPU engine7. |

reg_engine7_base_addr_5_l | 0x828 | 32 | r/w | The lower 32 bits of base address5 of DPU engine7. |

reg_engine7_base_addr_5_h | 0x82c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address5 of DPU engine7. |

reg_engine7_base_addr_6_l | 0x830 | 32 | r/w | The lower 32 bits of base address6 of DPU engine7. |

reg_engine7_base_addr_6_h | 0x834 | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address6 of DPU engine7. |

reg_engine7_base_addr_7_l | 0x838 | 32 | r/w | The lower 32 bits of base address7 of DPU engine7. |

reg_engine7_base_addr_7_h | 0x83c | 32 | r/w | The lower 12 bit in the register represent the upper 1 bit of base address7 of DPU engine7. |