LogiCORE XPS LL FIFO (v1.02a) Data Sheet(DS568) - 1.9 English - The XPS LL FIFO is a soft IP core designed for Xilinx FPGAs. This core allows memory mapped access to a LocalLink interface. The core can be used to interface to the XPS LL TEMAC without the need to use DMA. Other uses include interfacing to the LocalLink interfaces on PLBv46 PCIe and PLBv46 PCI. - DS568
xps_ll_fifo.pdf
- Document ID
- DS568
- Release Date
- 2011-02-28
- Version
- 1.9 English