LogiCORE IP LTE PUCCH Receiver v2.0 Product Brief (AXI)(XMP156) - 2.0 English - The Xilinx LogiCORE IP LTE PUCCH Receiver implements AXI4-Stream compliant, high-performance, optimized block for the 3GPP TS 36.211 v9.00 Physical uplink control channel. The data and control for the core are input on independent AXI4-Stream channels as slave interfaces and the resulting status is output on an AXI4-Stream master interface. - XMP156
xmp156_lte_pucch_rx.pdf
- Document ID
- XMP156
- Release Date
- 2013-03-20
- Version
- 2.0 English