Ethernet Cores Hardware Demonstration Platform (XAPP955) - Describes the functionality of the LogiCORE IP 10-Gigabit Ethernet and XAUI cores in Xilinx FPGA hardware. Development board requirements, setup instructions, MAC core-specific design components, and a description of the GUI used to control the demonstration platform are provided. - XAPP955
xapp955.pdf
- Document ID
- XAPP955
- Release Date
- 2008-09-19
- Revision
- 1.3 English