MMCM and PLL Dynamic Reconfiguration Application Note (XAPP888) - Provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Xilinx 7 series, UltraScale, and UltraScale+ FPGAs mixed-mode clock manager (MMCM). Similarly, the phase-locked loop (PLL) can be changed through the dynamic reconfiguration port (DRP).