Bitstream Identification with USR_ACCESS Application Note (XAPP497) - The USR_ACCESS register, present in the Virtex-5, Virtex-6, and all 7 series FPGAs, allows the ability to embed version information into a 32-bit fabric-accessible register at the bitstream generation phase. - XAPP497

Document ID

XAPP497

Release Date

2011-08-15

Revision

1.0 English