LVDS Source Synchronous 7:1 Serialization and Deserialization Using Clock Multiplication Application Note (XAPP1315) - Describes how to use ISERDESE3 and OSERDESE3 efficiently in conjunction with the mixed-mode clock manager (MMCM) or phase-locked loop (PLL) for reception and transmission of 7:1 data using low-voltage differential signaling (LVDS) data transmission at speeds from 415 Mb/s to 1,100 Mb/s per line.