Partial Reconfiguration of a Hardware Accelerator with Vivado Design Suite for Zynq-7000 AP SoC Processor (XAPP1231) - This application note describes the tool flow, concepts and techniques for Partial Reconfiguration on Xilinx? devices using the Vivado Design Suite through the device configuration (DevC) / processor configuration access port (PCAP) interface on a Zynq? All Programmable SoC.,This application note describes the tool flow, concepts and techniques for Partial Reconfiguration on Xilinx? devices using the Vivado Design Suite through the device configuration (DevC) / processor configuration access port (PCAP) interface on a Zynq-7000 All Programmable SoC device.,This application note describes the tool flow, concepts and techniques for Partial Reconfiguration on Xilinx? devices using the Vivado Design Suite through the device configuration (DevC) / processor configuration access port (PCAP) interface on a Zynq? All Programmable SoC.,This application note describes the tool flow, concepts and techniques for Partial Reconfiguration on Xilinx? devices using the Vivado Design Suite through the device configuration (DevC) / processor configuration access port (PCAP) interface on a Zynq? All Programmable SoC.