Asymmetric Lane Design with Aurora 64B/66B IP Core Application Note (XAPP1227) - Aurora 64B66B is a scalable, lightweight, high data rate, link-layer protocol for high-speed serial communication. Aurora is designed to enable easy implementation of Xilinx transceivers using an intuitive wizard interface. The Aurora protocol specification is open and available upon request. - XAPP1227
xapp1227-aurora-64b66b-asymmetric-lane-design.pdf
- Document ID
- XAPP1227
- Release Date
- 2015-11-03
- Revision
- 1.0.1 English