A Zynq Accelerator for Floating Point Matrix Multiplication Designed with Vivado HLS (XAPP1170) - Describes how to use Vivado HLS to develop a floating-point matrix multiplication accelerator connected via an AXI4-Stream interface to the ARM CPU ACP in the Zynq-7000 AP SoC. - XAPP1170
xapp1170-zynq-hls.pdf
- Document ID
- XAPP1170
- Release Date
- 2016-01-21
- Revision
- 2.0 English