Xilinx Spartan-6 FPGA DDR3 Signal Integrity Analysis and PCB Layout Guidelines (WP479) - SpartanĀ®-6 devices in conjunction with DDR2/DDR3 DRAMs provide significant memory interface bandwidth, flexibility, and power use efficiency, making them the ideal choice for system designers to address the demands of cost-sensitive, high-volume applications that require optimal performance. - WP479
wp479-ddr3-si-pcb.pdf
- Document ID
- WP479
- Release Date
- 2016-06-14
- Revision
- 1.0 English