Achieving High Performance DDR3 Data Rates (WP383) - This white paper describes various memory interface and controller design challenges and the high-performance solution that achieves a 1.866 Gb/s DDR3 data rate for Virtex-7 and Kintex-7 FPGAs, and Zynq-7000 AP SoCs. - WP383

Document ID

WP383

Release Date

2013-08-29

Revision

1.2 English