WP283 Using System Generator for Systematic HDL Deisng, Verification, and Validation - Using SystemGenerator, users can functionally simulate a design and use the MATLAB environment to verify the bit/cycle-tru model against the golden reference results, produced either externally or inside the MATLAB environemnt. - WP283
wp283.pdf
- Document ID
- WP283
- Release Date
- 2008-01-16
- Revision
- 1.0 English