Utility Reduced Logic (v1.00a) Data Sheet(DS482) - 1.6 English - The Utility Reduced Logic core applies a logic reduction function over an input vector to generate a single bit result. The core is intended as glue logic between peripherals. - DS482
util_reduced_logic.pdf
- Document ID
- DS482
- Release Date
- 2009-12-01
- Version
- 1.6 English