Virtex-7 FPGA VC7203 Characterization Kit IBERT Getting Started Guide (Vivado Design Suite 2015.1)(UG847) - 2015.1 English - This document provides a procedure for setting up the VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT) demonstration using the Vivado Design Suite. The demonstration shows the capabilities of the Virtex-7 XC7VX485T FPGA. - UG847
ug847-vc7203-ibert-gsg-vivado-2015.1.pdf
- Document ID
- UG847
- Release Date
- 2015-04-27
- Version
- 2015.1 English