LogiCORE IP Serial RapidIO v5.6 User Guide (UG503) - 5.1 English - The Serial RapidIO User Guide v5.6 provides information about the Xilinx LogiCORE IP Serial RapidIO core. The Xilinx LogiCORE RapidIO core is a fully verified, pre-implemented RapidIO Logical and Transport Layer. It is designed to support Verilog-HDL. The design examples in this book are provided in Verilog. - UG503
srio_ug503.pdf
- Document ID
- UG503
- Release Date
- 2011-07-29
- Version
- 5.1 English