LogiCORE IP RAM-based Shift Register v11.0 Data Sheet (DS228) - 11.1 English - The Xilinx LogiCORE IP RAM-based Shift Register core provides a very efficient multi-bit wide shift register for use in FIFO-like applications or as a delay line. Fixed-length shift registers and variable-length shift registers can be created. - DS228
shift_ram_ds228.pdf
- Document ID
- DS228
- Release Date
- 2011-02-28
- Version
- 11.1 English