ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-6 GTX Data Sheet(DS732) - 2.06a English - The ChipScope Pro IBERT core for Virtex-6 GTX transceivers can be used to evaluate and monitor GTX transceivers. The design includes pattern generators and checkers implemented in FPGA logic, and access to the ports and dynamic reconfiguration port (DRP) attributes of the GTX transceivers. - DS732
chipscope_ibert_virtex6_gtx.pdf
- Document ID
- DS732
- Release Date
- 2011-10-19
- Version
- 2.06a English