ChipScope Integrated Bit Error Ratio Test (IBERT) for Virtex-5 GTP Data Sheet(DS773) - 1.0 English - The ChipScope Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex-5 GTP is a customizable core that can be used to evaluate and monitor the health of Virtex-5 GTP Transceivers. The design includes pattern generators and checkers implemented in FPGA logic, as well as access to the ports and DRP attributes of the MGTs.