LogiCORE IP ChipScope Pro IBERT for 7 Series GTX Transceivers (DS872) - 2.02a English - The customizable LogiCORE IP ChipScope Pro Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTX transceivers is designed for evaluating and monitoring the GTX transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTX transceivers. - DS872
chipscope_ibert_7series_gtx.pdf
- Document ID
- DS872
- Release Date
- 2012-04-24
- Version
- 2.02a English